Alif Semiconductor /AE722F80F55D5AS_CM55_HE_View /ETH /ETH_MTL_INTERRUPT_STATUS

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Interpret as ETH_MTL_INTERRUPT_STATUS

Q0IS=Val_0x0, DBGIS=Val_0x0

Description

MTL Interrupt Status Register

Fields

Q0IS	Queue 0 Interrupt status This bit indicates that there is an interrupt from Queue 0. To reset this bit, the application must read Queue 0 Interrupt Control and Status register to get the exact cause of the interrupt and clear its source. 0 (Val_0x0): Queue 0 interrupt status not detected 1 (Val_0x1): Queue 0 interrupt status detected
DBGIS	Debug Interrupt status This bit indicates an interrupt event during the slave access. To reset this bit, the application must read the ETH_MTL_DBG_STS register to get the exact cause of the interrupt and clear its source. 0 (Val_0x0): Debug interrupt status not detected 1 (Val_0x1): Debug interrupt status detected

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